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Mohammad Hammoud |
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I am a Postdoctoral Research Associate at Carnegie Mellon University (CMU) in Qatar. I have a broad interest in computer systems with an emphasis on cloud computing and computer architecture. For my Ph.D. thesis, I focused on L2 cache design of multicore processors. After joining CMU in 2011, I extended my work to cloud computing where I devised multiple MapReduce scheduling techniques and optimized task parallelism for improved Hadoop performance. I hold a BS in Computer Science from the American University of Science and Technology, Lebanon, as well as MS and PhD in Computer Science from the University of Pittsburgh, USA. |
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Teaching At Carnegie Mellon University (CMU) in Qatar:
Prior to Joining CMUQ:
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Research Projects Scheduling in Hadoop: The dynamic nature of cloud infrastructure requires significant advancements in application workflow management and scheduling. In this research I am working towards improving scheduling mechanisms for applications running on the cloud. Specifically, I am working on applying data locality to Reduce task scheduling in Hadoop, thereby reducing network traffic and enhancing the performance of MapReduce jobs. I am also working on new monitoring and scheduling techniques to better detect faulty and slow tasks in MapReduce and intelligently alleviate their negative effects on the overall system performance. [CloudCom2011, CLOUD2012, Two Book Chapters on Virtualization and Data Analytics for the Cloud, Proposal Accepted, CRC Press] Workload Characterization: In a dynamic infrastructure environment such as clouds, it is critical to understand an application’s resource needs and behavior. This enables intelligent configuration of the incubating distributed analytics engines as well as effective provisioning of virtual resources that are tied to the needs of applications, among others. In this research I aim to characterize various scientific applications to influence provisioning, configuration as well as static and dynamic optimization for such applications on cloud computing systems. [In-Progress. Paper Submitted to CLOUD2013] Cloud Monitoring: Deploying performance-sensitive applications on the cloud is cumbersome due to the complexity of the application execution environment. Routine tasks such as monitoring, performance analysis and debugging often require close interaction and inspection of multiple layers in the application and system software stack. In this research I aim to design monitoring tools that help integrate metrics into these layers and allow for flexible visualization and analysis. [CloudCom2011] CMP Cache Management: As large uniprocessors are no longer scaling in performance, CMPs have become the trend in computer architecture. CMPs can easily spread multiple threads of execution across various cores. Besides, CMPs scale across generations of silicon process simply by stamping down copies of the hard-to-design cores on successive chip generations. A key requirement to obtaining high performance from CMPs is to effectively manage the limited on-chip cache resources. In this research I present a general framework for approaching cache management in CMPs and aim to explore novel CMP cache designs that effectively employ the framework and efficiently achieve scalable performance.[HiPEAC 2009, ICS 2009, CAL 2010, PhD Dissertation 2010, PACT 2010, HiPEAC 2011, JPDC 2011, Book Chapter Submitted to CRC Press] High-Performance Memory Substrates for Search-Intensive Applications: Search operations can occupy a significant portion of total execution time and energy consumption, while posing a difficult performance problem to tackle using traditional memory hierarchy concepts. In this research I aim to extend the conventional content addressable memory to accelerate search operations present in many important real-world applications (e.g., IP address lookup in core routers and trigram lookup in large speech recognition systems). [ISPASS 2007] Power-Aware Memory Management using Software Generated Hints: Current state-of-the-art power-aware DRAM chips offer various power modes (active, standby, nap, and powerdown) in order to provide a potential to limit power consumption in the face of increasing demand for performance. In response to workloads becoming increasingly memory-intensive and data-centric, in this research I aim to utilize and exploit various power modes for the most effective main memory power management. [Technical Report TR-09-163- Provided to Intel (Proprietary of Intel)] |
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Publications
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