Career Profile

I am currently pursuing Masters in Electronics and Computer Engineering at Carnegie Mellon University with focus on Computer Architecture and Machine Learning. Prior to masters, I worked at Synopsys for the verification of ARC processors. During this, I have been part of development of a System Verilog based pseudo random instruction sequence generator to automatically generate test cases for functional verification of ARC VDSP processor.

Professional Experience

Graduate Research Assistant

Sep 2016 - Dec 2016
Carnegie Mellon University, Pittsburgh

  • Implemented a design of Matrix-Matrix multiplication for FPGA acceleration on the infrastructure of Microsoft Catapult.
  • Identified a crucial issue caused due to synthesis tool optimization with unconnected pins.

ASIC Digital Design Engineer

Apr 2015 - Jul 2016
Synopsys Inc, Hyderabad

  • Developed a verification tool for generating pseudo random instruction sequences using object oriented System Verilog for the verification of DesignWare ARC HS line of processors, specifically for HS VDSP vector super-scalar processor
  • Worked on verification of DesignWare ARC EV Sub system that is based on ARC HS processors

Graduate Technical Intern

Jul 2014 - Apr 2015
Synopsys Inc, Hyderabad

  • Debugged System level regressions for the verification of DesignWare ARC HS38 processor.

Undergraduate Technical Intern

Jul 2013 - Dec 2013
Intel Corporation, Bangalore

  • Root caused complex bugs in UoIP core that involved interaction with application layer and provided smart fixes for multiple bugs.

Undergraduate Technical Intern

May 2012 - Jul 2012
Steel Authority of India Limited, Bhadravati

  • Studied the development of a closed loop feedback system for Controlling the lance in BOF using PLC.


Carnegie Mellon University

Designed and Implemented a performance optimized Convolutional Neural Network IP using Xilinx Vivado HLS. Integrated the IP with AXI interfaces using Xilinx Vivado Design Suite for digit classification of MNIST images. Achieved over 2x acceleration compared with execution on ARM.

Carnegie Mellon University

Identified the key research topics in computer science by generating TFIDF of publications over past few decades. Analyzed the time trends of these key topics to notice important historical breakthroughs and current hot research areas.

Design of a General Purpose Microprocessor

Spring 2014
Birla Institute of Technology and Science, Pilani

Implemented an 8-bit microprocessor using Verilog HDL with control unit having 8 instructions in ISA. Developed the ALU block using Kogge-Stone full adder design and synthesized the design with RC compiler

Hardware Partitioning for Implementation on Partially Reconfigurable

Spring 2014
Birla Institute of Technology and Science, Pilani

Developed and Implemented a Genetic algorithm in PERL to derive optimized partitions of some functions to be executed on a FPGA

Designed a 32KB SRAM Peripheral Circuitry

Spring 2014
Birla Institute of Technology and Science, Pilani

Designed a 8:256 decoder using Dynamic domino logic. The schematic and layout of the design have been made in Cadence-Virtuoso software

Skills & Proficiency

Verilog & System Verilog

C & C++