Projects
Logic Design: Bus Interface
This project implemented a bus protocol between a simple processor and memory unit. The processor was
capable of issuing read and write commands for 8-bit data packets across a bus two one of two memory
modules. Timing was a big issue in this lab as the memory module needed to be able to handle commands
with little to no delay between the address and data to be written.
This project was written in
SystemVerilog and was submitted for grading on the 1st of March, 2011.