I am a second year Ph.D. student in Electrical & Computer Engineering at Carnegie Mellon University. I am currently a part of the Advanced Chip Test Laboratory (ACTL), advised by Professor Shawn Blanton.
I graduated with a B.S. in Electrical & Computer Engineering and a minor in Linguistics at CMU in 2015, and I will be obtaining my M.S. in Electrical & Computer Engineering at CMU in May 2017. Over the years at CMU, I have gained knowledge not only in chip testing and diagnosis, but also in a diverse array of areas including machine learning, signal processing, and embedded systems.
When ECE work is not taking over my life, I organize and/or participate in outreach and mentoring programs. Besides that, I spend my time watching and critiquing films, catching up on politics, pondering linguistics, or devouring a juicy T-bone steak.
My current research interests include:
(1) machine learning on tester and simulation data to improve diagnosis resolution,
(2) test and diagnosis of Altera FPGA's routing resources, and
(3) adaptive test and diagnosis of logic and interconnect resources of FPGAs.