I am a PhD student in Electrical and Computer Engineering Department of Carnegie Mellon University. My advisors are James Hoe and Franz Franchetti. I am currently affiliated with CALCM and SPIRAL labs.
My research interests include computer architecture, hardware design, DSP and FPGA-based computing. I am particularly focusing on memory subsystem modeling and optimization.
I have been working on developing algorithms and architectures for DSP transforms targeting memory bandwidth optimizations for FPGAs (see this).
Currently I am trying to generalize my previous work. I am trying to build a framework that captures both application (e.g. DSP transform) and hardware (e.g. DRAM or on-chip memory etc.) in the same formal model. Given the application parameters and hardware resources, the framework automatically determines the algorithm and hardware optimizations for the best performance and power efficiency. Output generated by the framework can be the full system represented in HDL ready for synthesis or it can be targeted for custom computing platforms (e.g. custom FPGA processors, CoRAM etc.).
I did a summer internship at Oracle, Santa Clara, CA, from May to August 2012, where I worked on the memory subsystem of the next generation SPARC processors.